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V.22bis 2400 bps Full Duplex Modem

Note that this document is not actually the V22bis standard or a copy thereof. I have designed this document to not violate copyright but to make the content of the standards available to a wide audience.

The title of the standard is 2400 bits per second duplex modem using the frequency division technique standardized for use on the general switched telephone network and on point-to-point 2-wire leased telephone-type circuits.

It was originally approved in 1984 at Malaga-Torremolinos, and must have been written before then. It has been ammended in 1988 in Melbourne and I dont know what has happened to it in 1992.

Consideration

The CCITT notices that there is a demand for data transmission at the rate and method indicated in the title, that is at 2400 bps full duplex.

There is a requirement to have a fall back speed, and why not use the V.22 recommendation?

Frequency division method is used to separate the two directions used in the full duplex data transmission. This is actually a for of frequency division multiplexing whereby two channels are transmitted on different frequencies.

Declaration

The CCITT are not too sure about this and this is only a provisional modem characteristics specification.
  1. Introduction

    The introduction says where the modems are to be used, that is on The general switched telephone network (PSTN analogue service) and also on point to point two wire leased lines. The main features of the modems using V.22bis are:
    1. The modems use full duplex
    2. frequency division multiplexing is used to separate out the send and receive channels
    3. The nominal transmit line speed is 600 baud
    4. Quadrature amplitude modulation is used on each channel.
    5. A scrambler is used
    6. An adaptive equaliser is included
    7. A compromise equaliser is included
    8. There are test facilities
    9. Data signalling can be synchronous or start-stop
    10. Bit rates can be either 2400 or 1200 bits per second.
    11. It has automatic bit rate recognition
    12. When operating at 1200 bits per second V.22bis is the same as V22.
    13. There are places in the world where these modems are ilegal!
  2. Line Signals

    1. frequencies for carrier and guard tones

      There are two channels are high and a low channel. The channels are compulsory. For the low channel the carrier is 1200 Hz with an allowed deviation of one half a Hertz. (+/- 0.5 Hz). For the high frequency channel the carrier is 2400 Hz with an allowed deviation of one Hertz (+/- 1 Hz).

      Guard tones are optional. They may be used with the high channel only. Certain countries will specify their use. In Australia we are not allowed to use guard tones. The alternative guard tones are 1800 Hz and 550 Hz. Deviation of the guard tone is allowed upto 20 Hertz up or down in frequency.

    2. Signal levels for data signals

      A 1800 Hz guard tone will be from 5 to 7 dB below the high channel data signal in power. A 500 Hz guard tone will be from 2 to 4 dB below the high data channel signal level. A guard tone will sap power from the data signal so the high channel signal is about 1 dB below the power of the low channel data signal.
    3. Compromise Equaliser

      The modem transmitter shall use a fixed compromise equaliser. What's that?
    4. Characteristics of the group delay and spectrum

      The group delay for the transmitter in the frequency ranges 900-1500 Hz and 2100-2700 Hz must be within plus or minus 150 microseconds.

      The amplitude of the transmitted frequency spectrum excludes the compromise equaliser effect and is given by a mathematical expression and a graph. The same graph is use for the low and high channel. The spectrum graph is symmetrical about the carrier frequency, so I will describe it in terms of offset from the carrier frequency:

           frequency range    dB                  Frequency range     dB
           0 - 125            -0.75               0 - 125             0.75
           125 - 300          -0.75 to -4          125 - 300           0.75 to -2
           300 - 400          -4 to -9            300 - 400           -2 to -5     
           400 - 475          -9 to -20           400 - 450           -5 to -9
                                                  450 - 550           -9 to -20
        
    5. Modulation - Signalling rates

      There are two data rates 2400 or 1200 bits per second. The symbol rate sent is 600 baud. The required accuracy is within one part in ten thousand. (+/-0.0001)
    6. Modulation data bit Encoding at 2400 bps

      The data stream as it comes out of the scrambler is used to modulate the carier using QAM. The data is divided into quadbits - that is groups of four bits. The first two bits in time are separated out and used to select the next quadrant of the QAM signal. This is done by associating an angle with each dibit that is added to the previous quadrant to get the next quadrant.

          first   second        quadrant    number to add        new quadrant number
          bit     bit    dibit  angle       to quadrant number   (previous number) 
                                change      modulo four          (1  2  3  4)
          0       0      00     90          1                     2  3  4  1 
          0       1      01     0           0                     1  2  3  4
          1       1      11     270         3 (-1)                4  1  2  3
          1       0      10     180         2                     3  4  1  2
      
      
         00   !   01
              !
        ------+-------
              !
         10   !   11
      
         formula
      
         new quadrant number = (old quadrant number + first bit *2 + second bit eor first bit) mod 4
        

      The third and fourth bits in the quad bit are used to select one of the points in the quadrant that was selected by the first dibit. These bits are the tird and fourth in time and constitute the second dibit. Each quadrant contains the same pattern, but is rotated into position so quadrant 1 is off by 0 degrees, quadrant 2 by 90 degrees etc. Dibit 00 selects the point closest to the origin and so is the lowest power. Dibit 11 selects the point farthest from the origin having the highest power. Dibit 01 is the most behind in phase and dibit 10 is the most leading in phase. The table below summarises.

        dibit       coordinates  amplitude   phase power
                     X     Y 
        00           1     1     r(2) 1.414   45     2
        01           3     1     r(10)3.162   18.43  10
        11           3     3     r(18)4.242   45     18   
        10           1     3     r(10)3.162   71.57  10
      
      
        quadrant 2                      quadrant 1
                              |
             11.       01.    +3   .10       .11
                              !
                              !
                              !
                              |
             10.       00.    +1   .00       .01
              -3        -1    !   +1        +3
          -----+---------+----+----+---------+------
                              |
             01.       00.    +1   .00       .10
                              !
                              !
                              !
                              |
             11.       10.    +3   .01       .11
                              |
         quadrant 3                    quadrant 4
      
        
    7. Modulation data bit Encoding at 1200 bps

      The data stream as it comes out of the scrambler is used to modulate the carier using PSK. The data is divided into dibits - that is groups of two bits. The first two bits in time are used to select the next quadrant of the PSK signal. This is done by associating an angle with each dibit that is added to the previous quadrant to get the next quadrant.

          first   second        quadrant    number to add        new quadrant number
          bit     bit    dibit  angle       to quadrant number   (previous number) 
                                change      modulo four          (1  2  3  4)
          0       0      00     90          1                     2  3  4  1 
          0       1      01     0           0                     1  2  3  4
          1       1      11     270         3 (-1)                4  1  2  3
          1       0      10     180         2                     3  4  1  2
      
      
         00   !   01
              !
        ------+-------
              !
         10   !   11
      
         formula
      
         new quadrant number = (old quadrant number + first bit *2 + second bit eor first bit) mod 4
        

      The signal elements used in each quadrant is that for 01 in the 2400 bps case. This results in two things appening. First the average power transmitted is the same for 1200 bps as it is for 2400 bps, and second the signal transmitted is the same as it would be for V.22.

      
        quadrant 2                      quadrant 1
                              |
                         .    +3    
                              !
                              !
                              !
                              |
                              +1             .
              -3        -1    !   +1        +3
          -----+---------+----+----+---------+------
                              |
               .              +1    
                              !
                              !
                              !
                              |
                              +3   .       
                              |
         quadrant 3                    quadrant 4
      
        
    8. Tolerance of receiver to frequency offset

      The receiver in a modem has to tolerate carrier frequency offsets of upto seven Hertz above or below the specified frequency. Given that the transmitter is allowed to be 1 Hz out, this allows the channel to introduce an offset of siz Hertz.
  3. Digital Data Interfaces

    1. Circuits that are compulsory

      the modem must provide the following circuits: signal ground, transmit data, receive data, request to send, clear to send, dataset ready, data terminal ready, data carrier detect, and ring indicator, rate selector, transmit clock, receive clock, external clock, loopback or test, local loopback, test indicator.

    2. Optional Circuits

      High speed indicator.
    3. Clear to Send Response Time

      CTS response time is the time taken for CTS to appear after RTS is asserted by the DTE. For ON to Off or OFF to ON response time must be less than 3.5 milliseconds.
    4. Data Carrier Detect Response Time

      DCD response time for loss of carrier is 40 to 65 milliseconds. When in fall back mode at 1200 bps the DCD response time is allowed to drop to 10 to 24 milliseconds as specified in V.22. When detecting carrier the handshake sequence listed below results in DCD ON. But if it is not the initial hand shake but after a dropout, then DCD will reappear 40 to 205 milliseconds after the signal exceeds the threshold.
    5. Data carrier detect threshold

      If the received signal from the line is greater than -43 dBm DCD should be ON.

      If the received signal from the line is less than -48 dBm, DCD should be OFF.

      The OFF to ON signal transition level must be at least 2 dB higher than the level for an ON to OFF transition, otherwise the behaviour between -48 dBm and -43 dBm is not specified. This measurement is done while the modem is receiving scrambled ones.

      Modems may also be desensitised!

    6. Guard Tones are not allowed to trigger the DCD signal!
    7. Rate Select

      The V.22bis modem can operate at two speeds. How is this controlled? One way is to use a switch. Another way is to use the Rate Select signal. The CCITT called this circuit 111. This control line is provided by the DTE, received by the modem and is optional. A high state indicates higher speed at 2400 bps and the low state indicates use the lower speed of 1200 bps.
    8. Electrical Characteristics (physical Interface)

      The V.28 recommendation is reccommended for electrical characteristics of the digital circuits. The pin assignment in ISO 2110 is recommended. Study Group XVII will work on a new standard for a balanced, low circuit count, more efficient interface for DTE to DCE.
    9. Faults in Data Set Ready

      The DTE should treat a failure of DTE to mean that it is OFF. So a powered down modem Will be signalling that it is not ready!
    10. Faults in Request to Send

      . The modem should treat an absence (fault) of the Request to Send signal as meaning OFF. A fault will thus cause no request to send.
    11. Faults in Data Terminal Ready

      . The modem should treat an absence (fault) of the Data Terminal Ready (DTR) signal as meaning OFF. A fault will thus indicate that the DTE is not ready.
    12. Other faults

      Other circuits can either use 0 or 1 when a fault is noticed.
  4. Operation Modes

    There are four modes of operation in V.22bis. They are a combination of the two speeds ( 1200 and 2400 bits per second) and synchronous or asynchronous operation. The CCITT calls asynchronous "start-stop". The Asynchronous characters can have 8, 9 10 or 11 bits per character.
    1. Transmitter Synchronous

      The DTE sends data to the modem on the transmit data circuit, in time with the signal from the transmit clock or the external clock provided by the DTE. The scrambler scrambles the data and passes it to the modulator.
    2. Transmitter Asynchronous

      When in asynchronous mode the DTE sends data to the modem in the form of asynchronous characters at 2400 or 1200 bits per second. The asynchronous data is converted to synchronous stream as specified in Recommendation V.14. The synchronous stream is then processed as in the previous paragraph.
    3. Receiver Synchronous

      The received data from the line is demodulated according to the modulation specified before. Note that only the way the data is transmitted is given and it is up to the implementor to work out how to demodulate the data stream. The data is descrambled. Recommendation V.14 describes how the synchronous data is turned into asynchronous start stop characters. The data is output on the receive data line. Suddenly the modem finds that it can exceed the normal speed for the asynchronous. In the Basic signalling the intracharacter rate is allowed to be from normal speed to one percent high. In the extended signalling rate range the intracharacter bit rate is allowed to go from the nominal rate to 2.29% high. On an 11 bit character this would cause 25% distortion, which should still be bearable by the DTE receiver.
  5. Scrambler and Descrambler

    1. Scrambler

      The scrambler is self synchronising. It is a feedback shift register that is described by this polynomial:
            
          1+x^-14+x^-17
      
          Let I be the data sequence input
              D be the data output from the scrambler
              x be an operator that advances on bit time
              x^-1 is an operator that gives the value one bit time back
              x^-n is an operator giving the value n bit times in the past.
      
          D = I + Dx^-14 + Dx^-17
      
          
      A circuit is added to detect a sequence of 64 consecutive one bits coming out of the scrambler. When this is detected an inverter inverts the next input going into the scrambler and reset the count to 64 again.
          
      
                                       +----+  +----+     +----+  +----+    +----+  +----+  +----+  
                 D <-----+-------<+>-->|x^-1|->|x^-1|->...|x^-1|->|x^-1|-+->|x^-1|->|x^-1|->|x^-1|
                         V        ^    +----+  +----+     +----+  +----+ |  +----+  +----+  +-+--+
                   +-----+-----+  |                                      |                    |
                   | Detector  |  |                                      |                    |
                   +-----+-----+  |                                      |                    |
                         V        |                                      |                    |
                    +---------+ +---+<-----------------------------------+                    |
          Input---->+Inverter +>+ + +<--------------------------------------------------------+
                    +---------+ +---+
      
        
    2. Descrambler

      The descrambler is self synchronising like the scrambler. It uses the same polynomial as the scrambler of 1+x^-14+x^-17. The data output from the demodulator is put into a shift register. Two selected bits are extracted and exclusive ored with the demodulator output to give the descrambler output.
          Let I be the data sequence input
              O be the data output from the descrambler
              x be an operator that advances on bit time
              x^-1 is an operator that gives the value one bit time back
              x^-n is an operator giving the value n bit times in the past.
      
          O = I + Ix^-14 + Ix^-17
      
          
      A circuit may be included that detects a sequence of 64 one bits continuously entering the scrambler. If it is detected the inverter will invert the next bit coming out from the descambler.It is a bit suspiscious that this circuit is optional. You can expect that it will cause an error once in 2^64 bits if it were not present in a random bit stream. This would happen naturally once in 256 megayears. However it can be artificially induced if the data is specially constructed. In fact once the shift register if full of ones futher ones coming in will keep it full of ones. This will happen naturally in asynchronous working when there are no characters being sent. So the only fluke is to get the shift register full of ones. This happens more frequently and would happen every 54 seconds on average with a random bit stream.

      
                                       +----+  +----+     +----+  +----+    +----+  +----+  +----+  
            Input ->-----+-------<+>-->|x^-1|->|x^-1|->...|x^-1|->|x^-1|-+->|x^-1|->|x^-1|->|x^-1|
                         V        |    +----+  +----+     +----+  +----+ |  +----+  +----+  +-+--+
                   +-----+-----+  |                                      |                    |
                   | Detector  |  |                                      |Input*x^-14         |
                   +-----+-----+  |                                      |                    |
                         V        v                                      |                    |
                    +---------+ +---+<-----------------------------------+        Input*x^-17 |
          Output<---+Inverter +<+xor+<--------------------------------------------------------+
                    +---------+ +---+
      
        
  6. Operating Sequence

  7. Test Facilities


Graeme Bartlett 4 December 1995